The bit error rate of a digital signal is the number of bits received incorrectly divided by the total number of bits received. A Bit Error Rate Tester (BERT) is a piece of equipment designed to calculate the bit error rate of a communication medium. The typical method of bit error rate testing is to produce a pseudorandom-binary sequence that can be transmitted over a fiber optic line and verified on the receiving end. The current equipment for bit error rate testing of 10 Gbps fiber optic data equipment is generally large, labbench-based equipment which is not feasible for use in the field. Utilizing current FPGA technology, the design, and the manufacture of BERT equipment for 10 Gbps fiber optic data lines that is compact enough for field use should be feasible. This thesis investigates prevailing methods for bit error testing and compares them for relative strengths and weaknesses. Based on this analysis, a proposed process will allow BERT implementation in a compact package. Successful development and implementation of this design will facilitate the productization of a portable and cheaper alternative to the more expensive and stationary desktop BERTs in current use.